The present invention relates to photolithographic processes and masks such as are used for the fabrication of semiconductor devices and, more particularly, to photolithographic processes and masks for printing sub-micron sized features on a substrate.
In existing optical photolithographic processes, a photolithographic mask, having various patterns that are to be printed on a substrate, is illuminated by a light source. The light is transmitted through the openings in the mask and collected by a projection lens that images the mask patterns onto a wafer or other substrate located at the image projection plane, typically at a predetermined reduction ratio. The focused image exposes one or more photoresist layers that were previously coated onto the wafer, and the exposed resist is then developed using a developer solution. The developer removes the exposed portions of the resist layer when a positive resist is used and removes the unexposed portions of the resist when a negative resist is used. As a result, the mask pattern is essentially transferred onto the resist and may be used to mask subsequent etching or doping steps.
As newer generations of denser and/or faster devices are introduced, smaller sized features must be printed on the surface of the wafer, extending the limits of optical photolithography. The optical photolithographic systems and the photoresists are required to operate in regions of non-linear behavior, which often degrades the control of critical dimensions of the printed features. Further, as the feature sizes approach or become smaller than the wavelength of the light source used to illuminate the mask, optical distortions are introduced in the printed patterns. The optical distortions cause printed line edge variations that are dependent on the density, size and location of adjacent features. The line edge variations often result in line length contraction, known as line shortening, which can bring about increased contact resistance as well as open circuits. The line edge variations can also cause the corners of printed features to round off, known as corner rounding, which can lead to uncontrolled changes in resistance along critical circuit paths.
A known approach for addressing these problems is to adjust the illumination conditions used when exposing the mask, such as adjusting the spatial coherency, the angle of illumination, the degree of defocusing and the exposure time. However, the optimal illumination conditions for reducing line shortening and corner rounding are often not the best conditions for the resolution of the printed features.
Another existing approach is to adjust the mask bias. The edges of the features on the mask are extended to compensate for the line shortening or corner rounding in the printed pattern on the wafer. However, as the device density grows and the feature sizes further shrink, there is often insufficient room between adjacent features on the mask to extend the edges to sufficiently compensate for these variations.
An additional known approach is to add shapes, known as serifs, to the mask pattern to add or subtract light in the areas where line shortening or corner rounding occurs which compensates for the shortening or rounding. This technique has the drawback, however, that the serifs are very small and make mask inspection and writing very difficult. Moreover, each feature may require multiple serifs, thereby greatly increasing the data that must be stored in the mask writing system when preparing such a mask. Additionally, the use of serifs becomes less effective as feature sizes decrease.
A further known alternative is described in U.S. Pat. No. 6,451,490 B1, titled “Method To Overcome Image Shortening By Use Of Sub-Resolution Reticle Features” to W. H. Advocate, et al., the disclosure of which is incorporated herein by reference. To address the problem of image shortening of dense array patterns, features smaller than the resolution capability of the photolithographic system, known as sub-resolution features, are added to the mask pattern and are oriented perpendicular to at least one feature of the dense array pattern. The sub-resolution features have a smaller width than that of the feature of the array pattern and do not print on the wafer. The sub-resolution features shown, however, are either located in the spaces between the features of the dense array pattern or bisect the features of the dense array pattern and therefore do not significantly reduce corner rounding and are not optimally located for minimizing line shortening.
It is therefore desirable to reduce the line shortening or corner rounding in a printed feature in a manner that avoids the above drawbacks.